In many programmable electronic and electrical devices it is desirable to convert a digital signal into an analog signal. A new DAC was developed and described in commonly assigned U.S. Pat. No. 5,041,831, entitled "INDIRECT D/A CONVERTER", and issued on Aug. 20, 1991 to Bohley et al., which is hereby incorporated by reference. In the above-mentioned '831 Patent, a plural channel indirect DAC is supplied with data words containing address bits and data bits, which are entered into a specific one of the converter's channels under control of the address bits of the data word. The data bits are applied to a binary rate multiplier of the channel which generates a pulse modulated output signal representing the binary value of the received data bits. The pulse modulated output signal is applied to an associated filter which converts the pulse modulated output signal to an analog output signal whose amplitude represents the binary value of the received data bits. Gating circuitry ensures that each output pulse is of a precisely controlled pulse width.
In a particular application, the indirect DAC has 16 output channels, although the indirect DAC may have a greater or fewer number of channels depending upon application. Each of the 16 channels are 16-bit DACs. If all 16 bits are used, the lowest frequency that will be filtered is 10 MHz/2.sup.16, or 10 MHz/65536, or 152.6 Hz. When used as a 12-bit DAC, the lowest frequency to be filtered is 10 MHz/2.sup.12, or 10 MHz/4096, or 2.441 kHz. It is desirable to tailor each output filter to match the lowest frequency to be filtered so as to minimize the settling time when going from one DAC setting to the next. Using the minimum number of data bits for a DAC channel for the particular application is desirable to help minimize the filter settling time.
One of the DAC channels is used to calibrate the output level of the filters. This channel is referred to as the reference loop. The number of data bits applied to the different channels may need not be the same and may vary in number from a minimum of 1 to a maximum of m.
A drawback in the above-mentioned indirect DAC is that it divides the input clock by 2 before using it for the DAC channels. This clock division is unnecessary since only the period of the clock is used for timing. Unfortunately, this condition doubles the settling time of all the DAC filters since they could have been running at 20 MHz (the integrated circuit process limit) instead of 10 MHz.
Another drawback of the above-mentioned DAC is that it requires one of the DAC output channels be used to supply the filter that comprises the reference loop, the output of which is used to calibrate the output level of the remaining filters on the remaining DAC channels.
Another drawback of the above-mentioned DAC is that, depending upon the number of bits with which the reference channel is programmed (i.e., the number of bits programmed to 1s), there will be a different offset voltage present on each of the other channels. This different offset voltage occurs because the above-mentioned DAC does not behave like a conventional DAC when the reference channel is programmed to all 1s (a hexadecimal code of FFFF for a 16-bit DAC).
When all 1s are programmed in the reference loop, the digital output is high for 65535 counts of the 10 MHz clock period, or 65535/10 MHz, or 6.5535 milliseconds (ms) and low for 1 count, or 1/10 MHz, or 100 nanoseconds (ns). The average voltage of this waveform is compared to the reference voltage, in this case 5V. This means that an all 1s input gives the reference voltage as output, not 1 q-level less than the reference voltage that would be expected from a conventional DAC. A q-level on a conventional 16-bit DAC would be equal to +5V/2.sup.16, or 5/65536, or 76 microvolts (.mu.V). In the indirect DAC with the reference loop programmed to all 1s for 16 bits, a q-level would be equal to +5V/(2.sup.16-1), or 5/65535, or 76 uV. In a 16-bit DAC, the error is insignificant, but it does cause the other DAC outputs to be 1/2 of a q-level high when programmed at mid-scale. This equates to a hexadecimal code 8000 which is a square wave, or (5/65535)(6553612), or 2.500038 V instead of the expected 2.500 V. If the reference channel is programmed for all 1s for 8 bits (hexadecimal code FF00), the error increases and would be equal to {5/(2.sup.8-1)}{(2.sup.8 /2)}, or (5/255)(256/2), or 2.509804 V not 2.500 V. This offset voltage error is particularly troublesome and confusing when the reference loop of different DACs have been programmed to different numbers of bits.
A third drawback is that the above-mentioned DAC is most accurate and exhibits the lowest drift with temperature on DAC channels that are operating under the same conditions as the reference loop, i.e. all 1s at 16 bits (if that is how the reference loop is programmed), or at full scale, +5V. Most DAC applications require a DAC to operate at or near mid-scale and be programmable above and below mid-scale. Generally it is desirable to have the highest accuracy and lowest drift near this mid-scale operating point. As mentioned above, this is not the case when the reference loop is programmed with all 1s. The 8 most significant bits of the indirect DAC simply vary the duty cycle of the clock divided by 2.sup.8, or 10 MHz/256, or 39.0625 kHz. Therefore, for all DAC codes on an 8-bit DAC, the digital output always operates at 39 kHz. In this instance, mid-scale would be a square wave and occur at 39 kHz for all DAC channels regardless of the number of data bits used since the DAC code would be 8000 for all channels. The rise and fall times and the number of transitions of the digital output also affect the offset voltage errors.
Therefore, it would be desirable to provide a way to program the reference loop (which in turn will calibrate all of the other DAC channels) such that whatever the number of input bits for each channel, an all 1s input will result in an output of one q-level below the reference voltage and a mid-scale code of 8000 (a square wave) will result in an output of 1/2 the reference voltage. Furthermore, it would be desirable for the most accurate and lowest drift to occur at the mid-scale output of the DAC (approximately 2.5V), and without using one of the DAC output channels as the input to the reference loop.